1. Field of the Invention
The present invention relates to a semiconductor device manufacturing method and semiconductor integrated circuit device and, more particularly, to a method of manufacturing a nonvolatile semiconductor memory device having stacked gate memory cells.
2. Description of the Related Art
As an example of the related art, manufacturing steps from the formation of element isolation regions (shallow trench isolations) to the formation of gate lines (word lines) of a memory cell array in a NAND nonvolatile semiconductor memory will be explained below.
FIG. 43 is a flowchart showing the well-known sequence from shallow trench isolation formation to word line formation. This sequence shown in FIG. 43 is illustrated in, e.g., FIGS. 2(a) to 2(d) of S. Aritome et al., “A 0.67-μm2 SELF-ALIGNED SHALLOW TRENCH ISOLATION CELL (SA-STI CELL) FOR 3V-only 256-Mbit NAND EEPROMS”, IEDM, pp. 61-64, 1994.
FIG. 44 is a plan view of the memory cell array formed following the procedure shown in FIG. 43. FIG. 45A is a sectional view taken along a line 45-45 in FIG. 44.
First, as indicated by ST1 in FIG. 43, a tunnel insulating film 5 is formed on a semiconductor substrate 4, and a floating gate (FG) conductor film 6 is deposited on the tunnel insulating film 5.
Then, as indicated by ST2, an element region (AA) mask pattern is formed on the floating gate conductor film 6, and used as an etching mask to dry-etch the floating gate conductor film 6 and semiconductor substrate 4, thereby forming shallow trenches in the semiconductor substrate 4 and separating the floating gate conductor film 6 in the bit line direction at the same time.
As indicated by ST3, an insulator (ST1) 9 is buried in the shallow trenches formed in the semiconductor substrate 4. Subsequently, an interpoly insulating film 10 that insulates floating gates from word lines is formed on the floating gate conductor film 6 and insulator 9. A word line conductor film 11 is deposited on the interpoly insulating film 10.
As indicated by ST4, a word line mask pattern 12 is formed on the word line conductor film 11, and used as an etching mask to dry-etch the word line conductor film 11, interpoly insulating film 10, and floating gate conductor film 6, thereby forming word lines WL and separating the floating gate conductor film 6 in the word line direction at the same time. FIGS. 45B and 45C illustrate this etching process. Note that similar to FIG. 45A, FIGS. 45B and 45C are sectional views taken along the line 45-45 in FIG. 44.
In these sectional views shown in FIGS. 45B and 45C, however, the floating gates 6 and insulating films 9 are actually tapered as shown in FIGS. 46A and 46B for the following reason. That is, due to the characteristics of dry etching for forming the shallow trenches in ST3, this etching progresses while depositing deposition films made of the etching product on the sidewalls. As shown in FIG. 46B, this taper forms, on the semiconductor substrate 4, portions hidden behind the insulating films 9 and interpoly insulating films 10. The floating gates 6 sometimes remain in these hidden portions without being etched. If these residues form, adjacent floating gates 6 shortcircuit. FIG. 47A is a plan view showing an ideal pattern (Design) of the floating gates (FG) 6 on the memory cell array. FIG. 47B is a plan view showing a pattern (Actual) of the floating gates (FG) 6 when the residues form.
If the residues form, as shown in FIG. 47B, the floating gates 6 do not form patterns independent of each other, but insufficiently separate from each other in the word line direction. Consequently, adjacent floating gates 6 connect to each other in the form of a chain along the bit line direction.